Experiments in Automating Hardware Veriication Using Inductive Proof Planning

We present a new approach to automating the veriication of hardware designs based on planning techniques. A database of methods is developed that combines tactics, which construct proofs, using speciic-ations of their behaviour. Given a veriication problem, a planner uses the method database to build automatically a specialised tactic to solve the given problem. User interaction is limited to specifying circuits and their properties and, in some cases, suggesting lemmas. We have implemented our work in an extension of the Clam proof planning system. We report on this and its application to verifying a variety of combinational and synchronous sequential circuits including a parameterised multiplier design and a simple computer microprocessor.